| Pin | Name | Function |
|---|---|---|
| 1 | Q5 | Decoded output 5 |
| 2 | Q1 | Decoded output 1 |
| 3 | Q0 | Decoded output 0 |
| 4 | Q2 | Decoded output 2 |
| 5 | Q6 | Decoded output 6 |
| 6 | Q7 | Decoded output 7 |
| 7 | Q3 | Decoded output 3 |
| 8 | GND | Ground (VSS) |
| 9 | Q8 | Decoded output 8 |
| 10 | Q9 | Decoded output 9 |
| 11 | Q4 | Decoded output 4 |
| 12 | CO | Carry Out - pulses high after every 10 clocks, for cascading |
| 13 | CI | Clock Inhibit - HIGH pauses counting, LOW enables it |
| 14 | CLOCK | Clock input - counter advances on rising edge |
| 15 | MR | Master Reset - HIGH resets counter to Q0 |
| 16 | VDD | Positive supply voltage |
Summary
CMOS decade counter/divider IC. Turns a stream of clock pulses into 10 sequential decoded outputs (Q0-Q9) — the classic partner for a 555 timer in LED chasers, sequencers, and simple event counters.
- Supply voltage (VDD): 3V - 15V (18V absolute max)
- Quiescent current: ~20µA @ 5V
- Outputs: 10 decoded outputs (Q0-Q9) + 1 Carry Out
- Max output power dissipation: 100mW per output transistor